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NeoPUF - Silicon Fingerprint

Native Physical Unclonable Function & Immutable Silicon Identity

Overview

iMQ Technology integrates advanced silicon Root-of-Trust (RoT) solutions to protect global edge devices and AI hardware. iMQ licenses patented NeoPUF technology from PUFsecurity across its product lineup—from the high-security SQ719x seriesto the flagship SQ813x Macan series. This endows every chip with a 2 Kb silicon fingerprint and an 8 Kb OTP secure storage and key extraction control space, providing a native, unclonable hardware identity.

Technical Architecture & Working Principle

1. What is PUF & NeoPUF's Mechanism

A Physically Unclonable Function (PUF) acts as a unique "silicon DNA" or fingerprint, converting tiny, random manufacturing variations into an unforgeable digital identity (0s and 1s). Unlike traditional SRAM PUFs that rely on transistor threshold voltage differences and suffer from environmental instability, NeoPUF utilizes quantum tunneling currents created by microscopic SiO₂ gate oxide variations. This quantum-level randomness remains completely permanent and stable under extreme operational conditions.

2. Four Pillars of Ideal PUF

Randomness (Hamming Weight = 50%): Perfectly balanced distribution of 0s and 1s for maximum key unpredictability.
Uniqueness (Hamming Distance = 50%): Ensures zero collision risk between any two chips
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Robustness (Bit-Error-Rate, BER = 0%): Silicon-proven zero error rate across extreme temperatures (-40°C to 125°C+) and voltage fluctuations, requiring no complex error-correcting codes (ECC).
Non-traceability: Microscopic quantum variations cannot be physically detected or extracted via advanced invasive inspection techniques (FIB, SEM, or TEM).

Business Value & Defense Scenarios

Native Silicon Root of Trust (UID & UHK): Generates zero-error Unique Identification (UID) and Unique Hardware Keys (UHK) on demand inside the chip, leaving no static digital traces when idle.
Invisible Key Protection: Dynamically decrypts sensitive credentials (such as Matter DAC certificates or cloud private keys) only within the secure boundary, shielding against flash memory dumps.

Ideal Static Entropy Source for TRNG: Serves as a high-speed (>100 Mbits/sec) and ultra-low power (<1 pJ/bit) static entropy source for TRNG, fully compliant with NIST SP 800-22 and SP 800-90B standards.

Hardware Digital Signatures (DID & C2PA): Provides an air-gapped hardware signature engine for Physical AI, AI Agents, and C2PA content authenticity frameworks.

Extended Reading

For deeper technical details on quantum tunneling PUF architecture, please refer to PUFsecurity NeoPUF Technical Document.

Anti-Tamper Designs

Silicon-Level Active Armor & Physical Defense for Edge Infrastructure

* NIST CMVP Level 3 Compliant

Overview

As edge computing, smart networking, and Physical AI devices deploy into increasingly accessible or unattended environments, traditional software-only security boundaries are no longer sufficient. Physical threats—such as chip decapsulation, micro-probing, side-channel power analysis, voltage/temperature glitching, and PCB bus eavesdropping—allow adversarial hackers to directly bypass host OS protections and extract critical private keys or intellectual property.

iMQ Technology integrates a Comprehensive Anti-Tamper Security Enclave directly into its silicon architecture. By combining active physical sensing grids, sub-microsecond dynamic key zeroization, SPA/DPA side-channel countermeasures, and encrypted I/O bus communication, iMQ delivers a 360-degree physical security boundary. This active defense mechanism guarantees that sensitive cryptographic assets remain completely immune to physical inspection, invasive reverse engineering, and fault injection attacks.

Technical Architecture & Working Principle

1. Multi-Tiered Physical Protection Layer (4 Sensor & Detection Technologies)

To counteract physical attacks—such as chip decapsulation, micro-probing, power manipulation, and laser fault injection—iMQ integrates four distinct hardware-level physical sensing mechanisms:

(a) Top-Layer Active Metal Shield: A high-density active serpentine metal grid covering the silicon surface. Any physical intrusion (e.g., decapsulation, FIB micro-probing, or mechanical grinding) severs or shorts the circuit, instantly triggering dynamic security responses.
(b) High Voltage Detection: Integrated voltage sensors continuously monitor operating power lines, instantly flagging adversarial over-voltage pulsing or power fault-injection attempts.
(c) High/Low Temperature Detection: Environmental thermal sensors detect extreme temperature manipulation (e.g., freezing or heating memory states to force instruction skips or bypass security checks).
(d) Laser Fault Injection Detection: Optical sensing circuits detect localized high-energy laser pulse attacks designed to induce transient bit-flips in internal registers during critical cryptographic operations.

2. Sub-Microsecond (<1µs) Dynamic Key Zeroization

Instant Key Zeroization (<1µs): Upon detection of physical tampering by environmental sensors or shield breakage, the hardware security controller triggers sub-microsecond key zeroization, instantly wiping secret keys and sensitive credentials in volatile registers before attackers can read memory state.
Host-Driven EraseKey Command (Command 0x91): Supports host-initiated emergency zeroization commands, allowing the main system to actively instruct the Secure Element to destroy critical keys in panic or intrusion scenarios.

3. Side-Channel & Glitch Attack Countermeasures

SPA/DPA Power Waveform Obfuscation: Integrates hardware power-masking and clock-jittering techniques to flatten power consumption profiles during cryptographic operations, preventing hackers from reconstructing secret keys via Simple or Differential Power Analysis (SPA/DPA).
Independent Internal Clock & Glitch Filtering: Driven by an independent internal oscillator isolated from external clock lines, shielding the cryptographic engine against clock-glitch attacks designed to bypass hardware verification loops.

4. Secure Channel & Zero-Backdoor Debug Security (Communication & OCD)

Secure Channel Communication (I2C / SPI): All data transmitted over host-to-SE communication interfaces (I2C and SPI) is fully encrypted using a hardware-established Secure Channel, eliminating plaintext exposure and preventing PCB bus eavesdropping or Man-in-the-Middle (MITM) hardware sniffing.
Zero-Backdoor OCD (On-Chip Debug) Security:
- Unbonded OCD Pins in Production: In production-grade chips, OCD test pins are physically unbonded and unexposed, preventing physical debug connection.
- Two-Layer Password Authentication: Engineering-stage OCD access is guarded by a strict two-layer cryptographic password barrier.
- Permanently Locked Backdoor Elimination: Once deployed in production, the debugging interface is permanently and irreversibly locked via one-time anti-tamper locks, guaranteeing zero hardware backdoors for physical access.

Business Value & Defense Scenarios

Immunity to Invasive & Reverse Engineering Attacks: Prevents decapsulation, micro-probing, and FIB circuit editing from compromising master root keys or proprietary algorithms.
Instant Threat Containment via Microsecond Zeroization: Guarantees that stolen or physically breached devices destroy sensitive credentials instantly, preventing key leakage in high-risk field deployments.
Side-Channel & Fault-Injection Resilience: Secures critical cryptographic computations even under adversarial power manipulation, voltage spikes, or extreme temperature tampering.
Compliance with Global High-Assurance Mandates: Fulfills physical security requirements under NIST FIPS 140-3 Physical Security Level 3/4, EU Cyber Resilience Act (CRA), and NDAA supply chain mandates for high-assurance assets.

Tiered Product Deployment Across iMQ SQ Series

SQ710x (Baseline Physical Security): Features Physical Protection 1.(a) (Active Metal Shield) combined with baseline hardware execution isolation.
SQ713x (Standard Anti-Tamper & Bus Defense): Features Physical Protection 1.(a) + 1.(b) (Active Metal Shield + High Voltage Detection), integrated Secure Channel (I2C/SPI) communication, SPA/DPA side-channel countermeasures, and host-driven EraseKey credential wiping.
SQ719x (Advanced Anti-Tamper Secure Element): Features Physical Protection 1.(a) + 1.(b) + 1.(c) (Metal Shield + High Voltage + H/L Temperature Detection), sub-microsecond (<1µs) dynamic key zeroization, and zero-backdoor OCD debug protection.
SQ813x Macan (Flagship Anti-Tamper & PQC Enclave): Equipped with Comprehensive Physical Protection 1.(a) + 1.(b) + 1.(c) + 1.(d) (Full-Suite: Metal Shield + High Voltage + H/L Temp + Laser Fault Injection Detection), independent internal clocking, sub-microsecond key zeroization, and native PQC engines.

Post-Quantum Cryptography (PQC)

Quantum-Safe Hardware Security for Next-Generation Infrastructure

Overview

With rapid advancements in quantum computing, traditional public-key cryptography—such as RSA and ECC (Elliptic Curve Cryptography)—faces severe vulnerabilities from quantum algorithms like Shor's algorithm. Under the emerging threat of "Harvest Now, Decrypt Later" (HNDL), sensitive data and authentication mechanisms transmitted today are at risk of future decryption if not preemptively upgraded.

Post-Quantum Cryptography (PQC) refers to cryptographic algorithms engineered to run on classical hardware while resisting attacks from quantum computers. By natively integrating internationally standardized PQC algorithms (such as NIST FIPS 203 and FIPS 204) at the silicon level and coupling them with a PUF-based Root of Trust (PUF-based RoT), PQC hardware solutions deliver future-proof, quantum-safe defense for long-lifecycle assets, enterprise systems, and edge computing platforms.

Technical Architecture & Working Principle

Our dedicated PQC hardware security architecture relies on advanced lattice-based cryptography integrated within an isolated hardware enclave. Its core technical highlighs include:

Lattice-Based Cryptography Acceleration: Mainstream NIST-standardized PQC algorithms rely on complex mathematical problems over high-dimensional lattices, demanding dedicated hardware acceleration for high efficiency:

FIPS 203 (ML-KEM): Designed for Key Encapsulation Mechanisms (KEM), enabling secure asymmetric key exchange over untrusted channels.

FIPS 204 (ML-DSA): Designed for Digital Signature Algorithms (DSA), providing high-assurance identity authentication and data integrity verification.
PUF-Enabled Entropy & Dynamic Key Generation: PQC algorithms require high-entropy random seeds and secure key generation. By fusing a Physical Unclonable Function (PUF) with a high-entropy True Random Number Generator (TRNG), secret keys are dynamically generated inside the isolated hardware enclave. Keys leave zero static digital traces in non-volatile memory at rest and vanish upon power-off, eliminating key cloning and physical reverse engineering at the silicon level.
Hybrid Cryptography & CNSA 2.0 Compliance: During the transition from classical to post-quantum security, a hybrid cryptographic architecture ("Classical RSA/ECC + PQC") is deployed for dual-layer key exchange. Fully compliant with NSA CNSA 2.0 specifications alongside classical cryptography (ECC P-521, RSA-4096, AES-256, SHA-3), ensuring seamless backward compatibility and robust security.

Business Value

Mitigating "Harvest Now, Decrypt Later" (HNDL) Threats: Prevents sensitive commercial IP, enterprise secrets, and long-lifecycle asset data from being intercepted today and decrypted by future quantum computers.
Pre-Certified Security Compliance: Built upon pre-certified PQC hardware modules compliant with NIST FIPS 203/204 and NSA CNSA 2.0, significantly slashing compliance testing timelines and certification costs for end products (accelerated time-to-market).
Easy-to-Integrate & Accelerated Performance: Dedicated hardware acceleration handles complex lattice matrix math off main processors, enabling host systems to achieve quantum resilience without software performance penalties or heavy host resource overhead.

Defense Scenarios & Key Applications

Enterprise Systems & Zero-Trust Architecture: Protects enterprise network communications, SSL/TLS 1.2/1.3 channels, PQC FIDO2 hardware security keys, and workstation identity authentication against quantum decryption attacks.

Physical AI & Edge Computing Platforms: Provides PQC-grade Secure Boot and Secure OTA firmware updates for Edge AI servers, humanoid robotics, and high-performance edge devices, safeguarding AI model intellectual property and preventing firmware tampering.

Critical Infrastructure & Long-Lifecycle Assets: Deployed in smart grid meters, industrial PLC controllers, and networking gateways required to operate securely in the field for 10 to 20+ years, ensuring lifelong immunity against quantum computing threats.